1. Field of the Invention
The invention relates generally to an integrated circuit (IC) isolation structure and more particularly to limited width trench isolation structures which are used to isolate devices of an IC.
2. Description of the Related Art
Various isolation structures are available to isolate devices in integrated circuits. One isolation structure, developed using a conventional method known as trench etch and refill, is shown in FIG. 1. In the conventional method, trenches 61-63 are etched in respective field regions 120 and 220 of the active devices 100 and 200 and subsequently filled with a CVD oxide 50 to isolate the active devices 100 and 200.
One problem with the conventional method is that a phenomena known in the art as "dishing" occurs in the oxide regions above the trenches 61-63 during the formation of the isolation structure. The "dishing" of the oxide 50 is represented by non-planar surface of the oxide 50 in FIG. 1.
The conventional method is illustrated in further detail by FIGS. 2A-2F. A pad oxide layer 11 is thermally grown on the surface of a silicon substrate 10 having well regions 130 and 230 as shown in FIG. 2A. Next, a layer of CVD silicon nitride 12 is deposited on top of the pad oxide layer 11 as shown in FIG. 2B. A photo-resist mask layer (not shown) is then deposited on top of the nitride layer 12 and the region of the nitride layer 12 exposed through the mask layer is anisotropically dry etched to produce etched openings 14 through the nitride layer 12 (see FIG. 2C). The etched openings 14 define field regions which are subsequently etched to form isolation trenches 61-63 illustrated in FIG. 2D (also shown in FIG. 1). The remaining portions of the nitride layer 12 function as a mask during the etching step.
After the trench formation, a CVD oxide layer 50 of a thickness H, where H&gt;thickness of the nitride layer 12+thickness of the pad oxide layer 11+the height of the trench 62, is deposited above the remaining portions of the nitride layer 12 and the trenches 61-63. Basically, the main criteria is to make sure that the level of the CVD oxide layer 50 is above the level of the nitride layer 12.
The step of depositing the CVD oxide layer 50 is followed by a planarization technique. One technique may be direct polishing. The resulting structure after the step of polishing is illustrated in FIG. 2F which shows that the level of the oxide 50 at the center portions of the trenches 61-63 are lower in height than at the edge portions of the trenches 61-63. This phenomena is what is known in the art as "dishing" and, as shown in FIG. 2F, adversely affects the planarity of the IC.
An alternative conventional method is illustrated in FIGS. 3A-3H. Steps associated with FIGS. 3A-3E are identical to the steps described with respect to FIGS. 2A-2E and will not be repeated here. Planarization in the alternative conventional method is carried out by the use of a planarization mask 51 as shown in FIG. 3F. After the planarization mask 51 is applied, the CVD oxide layer 50 is etched and the planarization mask 51 is removed. The resulting structure is illustrated in FIG. 3G. The structure of FIG. 3G is then polished to yield the structure of FIG. 3H, which again shows the effect of "dishing."